1. Field of the Invention
The present invention is related to semiconductor manufacturing. More specifically, the present invention is related to a method and apparatus for determining an improved assist feature configuration in a mask layout using a process-sensitivity model.
2. Related Art
The dramatic improvements in semiconductor integration densities in recent years have largely been made possible by corresponding improvements in semiconductor manufacturing technologies.
One such semiconductor manufacturing technology involves placing assist features in a mask layout. Note that assist features can be printing (e.g., super-resolution assist features) or non-printing (e.g., sub-resolution assist features). In either case, assist features are meant to improve the depth of focus of the patterns on the mask layout intended to be printed on the wafer.
Present techniques for placing assist features typically use design rules, which place and size assist features based on combinations of feature width and spacing parameters. Note that these techniques are not directed towards optimizing the assist feature length for improving depth of focus for 2D features.
Furthermore, rule-based approaches can result in missed or sub-optimal placement and/or dimensioning of assist features. Additionally, large and complex layouts can require a large number of design rules, which can be very difficult to manage. Moreover, design rules can be overly restrictive which can prevent designers from being able to achieve the best device performance.
In addition, design rule based techniques are typically geared towards improving manufacturability of 1-D regions of a pattern. As a result, rule-based techniques are usually not effective for improving the depth of focus of 2-D regions in a pattern.
Hence, what is needed is a method and apparatus for determining the locations and dimensions of assist features in a mask layout without the problems described above.